This invention relates to the art of analog-to-digital (A/D) converters and digital-to-analog (D/A) converters.
Analog-to-digital converters (ADCs) are circuits used to convert signals from the analog domain, where the signals are represented by continuous quantities such as voltage and current, to the digital domain, where the signals are represented by numbers. These circuits can be implemented in a large number of ways. Established A/D conversion techniques include flash, delta-sigma (or sigma-delta), sub-ranging, successive approximation, and integrating.
ADC""s typically include an internal digital to analog (D/A) converter. The D/A converter may be comprised in a feedback loop in the ADC. One example of an A/D converter is an over-sampled A/D converter. Oversampled A/D converters, often denoted as xe2x80x9cdelta-sigma convertersxe2x80x9d or xe2x80x9csigma-delta convertersxe2x80x9d are well known in the art. A delta sigma (D/S) converter essentially digitizes an analog signal at a very high sampling rate (oversampling) in order to perform a noise shaping function. The digitized signal is provided to an internal D/A converter to produce an analog signal, which is then supplied through a feedback loop to be combined with the analog input signal.
FIG. 1 shows, in block diagram form, a D/S converter 10 commonly known in the art. The D/S converter 10 may be a single bit or multi-bit delta sigma converter. The D/S converter 10 includes a D/S modulator 12 connected to a digital filter and decimation circuit 14. The D/S modulator 12 includes a summing node 16, a filter 18, an A/D converter 20, and a D/A converter 22. The D/A converter 22 is connected to the output of the A/D converter 20 and operates to provide feedback to the summing node 16. The summing node 16 includes a pair of inputs, one being connected to the analog input signal Vin and the other being connected to the output of the D/A converter 22.
In operation, the output of summing node 16 is low-pass filtered by filter 18 and subsequently converted into a digital signal by A/D converter 20. The digital signal in turn is converted back into an analog signal by D/A converter 22 and subtracted from analog input signal Vin at summing node 16.
The D/S modulator 12 converts the input signal Vin into a continuous serial bit stream at a rate determined by sampling clock frequency, kfs. Due to the feedback provided by the D/A converter 22 the average value output by the D/A converter 22 approaches that of the input signal Vin if the loop has enough gain.
A multi-bit D/S converter provides benefits over a single bit D/S converter implementation. Namely, a multi-bit D/S converter provides more resolution and less quantization noise. Additionally, a multi-bit D/S converter is more stable than single bit D/S converter. However, the multi-bit D/S converter suffers from linearity errors introduced by the internal multi-bit D/A converter.
Linearity error is the inability of the multi-bit D/A converter to accurately translate a digital input value into an analog current or voltage. In other words, given a particular digital input, the resulting analog output of the multi-bit internal D/A converter 62 approximates the digital value but is not exactly equal to the digital value. In reality, the actual analog output differs from the digital input value by an amount equal to the linearity error.
FIG. 2 shows a graphical comparison of an ideal linear vs. non-ideal, non-linear multi-bit D/A converter. The horizontal axis represents the codes or multi-bit digital signals applied to the inputs of both types of multi-bit D/A converters, ideal and non-ideal. The vertical axis represents the analog signal output therefrom. Line L represents the transfer function of the ideal or linear D/A converter. Line NL represents the transfer function of the non-ideal or non-linear D/A converter. Variations between the two lines represent the linearity errors. The distance between points on a vertical line through both line L and the line NL represent the linearity error produced by the non-ideal D/A converter for a particular input code. For example, if digital code x is input to both the ideal D/A converter and the non-ideal D/A converter, the respective outputs would be YL and YNL. The difference in voltage xcex94Y represents the linearity error corresponding to digital code x. This linearity error is viewed as noise and degrades the ultimate signal to noise ratio of the D/S converter which contains the non-linear D/A converter. This linearity error is static in nature and independent of frequency and voltage.
The source of linearity errors can be traced to the internal current generators of the multi-bit D/A converter. FIG. 3 shows, in schematic form, a simplified D/A converter 70 employing a number of internal current generators 72. Each of the internal current generators 72 is selectively connected to an output node 74 via switches 76. Each switch 76 contains an input configured to receive one bit of the digital code inputted to the D/A converter 70. For example, switch SN-1 is controlled by the most significant bit of the input digital code. When the most significant bit is 1, the associated current generator is connected to summing node 74. Thus, given a particular digital input code, the output of one or more of the current generators 72 is connected to the summing node 74.
If the D/A converter 70 was ideal and contained ideal current generators, current would be generated therefrom in integer units. For example, if the D/A converter 70 of FIG. 3 was an ideal 3 bit D/A converter, and a digital code inputted thereto equaled 111, the three ideal internal current generators 72 would generate 4, 2, and 1 units of current, respectively. However, internal current generators are rarely ideal. Given an input code 111, the non-ideal set of current generators, for example, might generate 4.05, 1.98, and 1.01 units of current, respectively.
The linearity error produced by the internal current generators can be further traced to a variety of causes, chief of which is the inability of integrated circuit manufacturers to form, in silicon, current generators having identical geometries. Several other causes can be related to the linearity error. Over time and use, the internal current generators may wear differently. Moreover, temperature variations may occur between the internal current generators. In any event, the physical differences between internal current generators in a D/A converter, even though slight, can produce significant errors in the translation of a digital input code into an analog equivalent.
U.S. Pat. Nos. 5,781,137 and 5,781,138 describe a system and method which operate to calibrate the internal D/A converter of a multi-bit A/D converter to eliminate or otherwise reduce linearity errors in the multi-bit A/D converter. The technique disclosed in these patents includes applying a known analog waveform, such as a pure sine wave, to an input of the A/D converter, or to a portion of the A/D converter, and generating digital signals representative of the pure sine wave. A number of the digital signals output from the converter are recorded. These recorded digital signals contain hidden information regarding the linearity errors associated with the internal D/A converter of the A/D converter. The linearity error information can be extracted and used in deriving correction coefficients and constructing a linearity error correction circuit. The linearity error correction circuit then can be used to correct for linearity errors in the A/D converter.
The system and method described in the above patents operate to calibrate the internal D/A converter and remove linearity errors from the internal D/A converter. Once the internal D/A converter has been calibrated, it would be more desirable to more fully take advantage of the internal D/A converter for other purposes.
The present invention comprises an analog to digital (A/D) converter which includes A/D converter and D/A converter modes. The A/D converter includes an internal digital to analog (D/A) converter (DAC) that may be used in a feedback loop during A/D operations (in the A/D mode), and may be used as a stand-alone D/A converter in the D/A mode. The present invention also takes advantage of advanced calibration techniques available for the internal D/A converter of the A/D converter.
The A/D converter may include a summing node, a loop filter, a multi-bit internal A/D converter, and a multi-bit D/A converter which are comprised in a feedback loop. A processing unit may be coupled to the output of the internal A/D converter. The processing unit may provide an output to an acquisition memory in the A/D mode. The acquisition memory may in turn provide an output to a host computer.
The processing unit and/or a separate computer system may perform a calibration function in the A/D mode to generate linearity error correction information for correcting linearity errors in the internal D/A converter. The linearity error correction information may be used in configuring a linearity error correction device, such as a look up table, implemented by the processing unit. In the A/D mode, the processing unit may implement the linearity error correction and a decimation function during A/D conversion. In the D/A mode, the processing unit also may implement the linearity error correction as well as other functions during D/A conversion.
In the A/D mode, calibration may operate as follows. First, a known analog waveform, such as a pure sine wave, is applied to the ADC. The processing unit may operate to extract linearity error information and then construct a look up table (LUT) from the linearity error information. This LUT may then be used to correct for internal errors in the D/A converter. In each of the A/D mode and the D/A mode, the processing unit may implement correction using the calibration look-up table. Thus, in each of the A/D mode and the D/A mode, the internal D/A converter may have reduced linearity errors.
The A/D converter also may include a first switching element and a second switching element for configuring the A/D mode or the D/A mode. The first switching element receives the output from the internal ADC and receives an output from the processing unit (comprising the external DAC input) and selectively provides one of these input signals as an output to the internal DAC. The second switching element receives the output from the internal DAC and selectively provides an output to either the summing node or to an external DAC output.
In the A/D mode, the first switching element provides the output from the internal ADC as the input to the internal DAC, and the second switching element provides the output from the internal DAC to the summing node. This thereby enables normal operation of the feedback loop during analog to digital conversion.
In the D/A mode, the DAC input is provided to the processing unit. In the D/A mode, the processing unit may implement one or more of an interpolation filter, summation node, H(z) transfer function, a rounder and the linearity error correction LUT, wherein the linearity error correction LUT is configured in a feedback path. The processing unit receives the DAC input and processes the DAC input using the above elements. The processing unit provides an output through the first switching element as the input to the internal DAC. The second switching element provides the output from the internal DAC to the external DAC output.
This thereby enables the internal D/A converter to function as a D/A converter for external signals. In other words, whereas in prior art A/D converters the internal D/A converter of the A/D converter is used solely during analog to digital conversion, in the A/D converter of the present invention, the internal D/A converter, in conjunction with the processor, is also useable to perform digital to analog conversion functions for external signals. In addition, linearity error information can be extracted from the internal DAC and used in calibrating the internal DAC during both the A/D mode and the D/A mode.